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(R)
X4043, X4045
4k, 512 x 8 Bit
Data Sheet September 30, 2005 FN8118.1
CPU Supervisor with 4kbit EEPROM
FEATURES * Selectable watchdog timer * Low VCC detection and reset assertion --Five standard reset threshold voltages --Adjust low VCC reset threshold voltage using special programming sequence --Reset signal valid to VCC = 1V * Low power CMOS --<20A max standby current, watchdog on --<1A standby current, watchdog OFF --3mA active current * 4kbits of EEPROM --16-byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of EEPROM array with Block LockTM protection * 400kHz 2-wire interface * 2.7V to 5.5V power supply operation * Available packages --8 Ld SOIC --8 Ld MSOP --8 Ld PDIP * Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM
Watchdog Transition Detector WP SDA Data Register Command Decode & Control Logic VCC Threshold Reset logic Block Lock Control Protect Logic Status Register EEPROM Array 2Kbits 1Kb 1Kb
DESCRIPTION The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
Watchdog Timer Reset RESET (X4043) RESET (X4045) Reset & Watchdog Timebase
SCL
VCC VTRIP
+ -
Power-on and Low Voltage Reset Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X4043, X4045 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X4043S8-4.5A X4043S8Z-4.5A (Note) X4043S8I-4.5A PART MARKING X4043 AL X4043 Z AL X4043 AM PART NUMBER RESET (ACTIVE HIGH) X4045S8-4.5A PART MARKING X4045 AL VCC VTRIP RANGE (V) RANGE (V) 4.5-5.5 4.5-4.75 TEMP RANGE (C) 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 4.5-5.5 4.25-4.5 0-70 0-70 -40-85 -40-85 0-70 0-70 ADM DBA X4045P X4045P Z X4045P I X4045P Z I X4045 AN 2.7-5.5 2.85-3.0 -40-85 -40-85 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free)
X4045S8Z-4.5A (Note) X4045 Z AL X4045S8I-4.5A X4045 AM
X4043S8IZ-4.5A (Note) X4043 Z AM X4043M8-4.5A X4043M8Z-4.5A (Note) X4043M8I-4.5A ADA DAZ ADB
X4045S8IZ-4.5A (Note) X4045 Z AM X4045M8-4.5A ADJ
X4045M8Z-4.5A (Note) DBH X4045M8I-4.5A ADK
X4043M8IZ-4.5A (Note) DAU X4043P-4.5A X4043PZ-4.5A (Note) X4043PI-4.5A X4043PIZ-4.5A (Note) X4043S8* X4043S8Z* (Note) X4043S8I* X4043S8IZ* (Note) X4043M8 X4043M8Z* (Note) X4043M8I X4043M8IZ (Note) X4043P X4043PZ (Note) X4043PI X4043PIZ (Note) X4043S8-2.7A* X4043P AL
X4045M8IZ-4.5A (Note) DBE X4045PZ-4.5A (Note) X4045P Z AL X4045P AL X4045P AM X4045P Z AM X4045 X4045 Z X4045 I X4045 Z I ADL
X4043P Z AL X4045P-4.5A X4043P AM X4045PI-4.5A
X4043P Z AM X4045PIZ-4.5A (Note) X4043 X4043 Z X4043 I X4043 Z I ADC DAW ADD DAR X4043P Z X4043P X4043P I X4043P Z I X4043 AN X4045S8* X4045S8Z* (Note) X4045S8I X4045S8IZ (Note) X4045M8 X4045M8Z (Note) X4045M8I X4045M8IZ (Note) X4045P X4045PZ (Note) X4045PI X4045PIZ (Note) X4045S8-2.7A
X4043S8Z-2.7A* (Note) X4043 Z AN X4043S8I-2.7A* X4043 AP
X4045S8Z-2.7A (Note) X4045 Z AN X4045S8I-2.7A X4045 AP
X4043S8IZ-2.7A* (Note) X4043 Z AP X4043M8-2.7A X4043M8Z-2.7A (Note) X4043M8I-2.7A ADE DAY ADF
X4045S8IZ-2.7A (Note) X4045 Z AP X4045M8-2.7A AND
X4045M8Z-2.7A (Note) DBG X4045M8I-2.7A ADO
X4043M8IZ-2.7A (Note) DAT X4043P-2.7A X4043PZ-2.7A (Note) X4043PI-2.7A X4043PIZ-2.7A (Note) X4043P AN
X4045M8IZ-2.7A (Note) DBC X4045P-2.7A X4045P AN X4045P Z AN X4045P AP X4045P Z AP
X4043P Z AN X4045PZ-2.7A (Note) X4043P AP X4045PI-2.7A
X4043P Z AP X4045PIZ-2.7A (Note)
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FN8118.1 September 30, 2005
X4043, X4045 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X4043S8-2.7* X4043S8Z-2.7* (Note) X4043S8I-2.7 X4043S8IZ-2.7 (Note) X4043M8-2.7 X4043M8Z-2.7 (Note) X4043M8I-2.7 X4043M8IZ-2.7(Note) X4043P-2.7 X4043PZ-2.7 (Note) X4043PI-2.7 X4043PIZ-2.7 (Note) PART MARKING X4043 F X4043 Z F X4043 G X4043 Z G ADG DAX ADH DAS X4043P F X4043P Z F X4043P G X4043P Z G PART NUMBER RESET (ACTIVE HIGH) X4045S8-2.7* X4045S8Z-2.7* (Note) X4045S8I-2.7 X4045S8IZ-2.7 (Note) X4045M8-2.7 X4045M8Z-2.7 (Note) X4045M8I-2.7 X4045M8IZ-2.7 (Note) X4045P-2.7 X4045PZ-2.7 (Note) X4045PI-2.7 X4045PIZ-2.7 (Note) PART MARKING X4045 F X4045 Z F X4045 G X4045 Z G ADP DBF ADQ DBB X4045P F X4045P Z F X4045P G X4045P Z G VCC VTRIP RANGE (V) RANGE (V) 2.7-5.5 2.55-2.7 TEMP RANGE (C) 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 0-70 0-70 -40-85 -40-85 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP(Pb-free) 8 Ld PDIP 8 Ld PDIP
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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X4043, X4045
The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP, PDIP NC NC RESET VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
Pin (SOIC/MSOP/DIP)
1 2 3
Name
NC NC RESET/RESET No internal connections No internal connections
Function
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below VTRIP. It will remain active until VCC rises above the VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. RESET/RESET goes active on power-uppower-up and remains active for 250ms after the power supply stabilizes. RESET is an active high open drain output. An external pull up resistor is required on the RESET/RESET pin. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Serial Clock. The Serial Clock input controls the serial bus timing for data input and output. Write Protect. WP HIGH prevents writes to any location in the device (including the control register). Connect WP pin to VSS when it is not used. Supply Voltage
4 5
VSS SDA
6 7 8
SCL WP VCC
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FN8118.1 September 30, 2005
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PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/RESET allowing the system to begin operation. Low Voltage Monitoring During operation, the X4043/45 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the (RESET/RESET) signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor intructions namely, a Start, Clock Low, Clock High and Stop. (See Page 18) The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin HIGH. Figure 1. Watchdog Restart
.6s SCL 1.3s
SDA Start WDT Reset Stop
EEPROM Inadvertent Write Protection When RESET/RESET goes active as a result of a low voltage condition (VCC < VTRIP), any in-progress communications are terminated. While VCC < VTRIP, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory block lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VTRIP Programming The X4043/45 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4043/45 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.
Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
WP VP = 15-18V
01234567 SCL
01234567
01234567
SDA A0h 01h 00h
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Setting a VTRIP Voltage There are two procedures used to set the threshold voltages (VTRIP), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIP is 2.9 V and the new VTRIP is 3.2 V, the new voltage can be stored directly into the VTRIP cell. If however, the new setting is to be lower than the present setting, then it is necessary to "reset" the VTRIP voltage before setting the new value. Setting a Higher VTRIP Voltage To set a VTRIP threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIP threshold voltage to the VCC. Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP and a 00h Data Byte in order to program VTRIP . The STOP bit following a valid write operation initiates the programming sequence. WP pin must then be brought LOW to complete the operation. To check if the VTRIP has been set, first power-down the device. Slowly ramp up VCC and observe when the output, RESET (4043) or RESET (4045) switches. The voltage at which this occurs is the VTRIP (actual) (see Figure 2). CASE A Now if the desired VTRIP is greater than the VTRIP (actual), then add the difference between VTRIP (desired) - VTRIP (actual) to the original VTRIP desired. This is your new VTRIP that should be applied to VCC and the whole sequence should be repeated again (see Figure 5). CASE B Now if the VTRIP (actual), is higher than the VTRIP (desired), perform the reset sequence as described in the next section. The new VTRIP voltage to be applied to VCC will now be: VTRIP (desired) - (VTRIP (actual) - VTRIP (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIP Voltage In order to set VTRIP to a lower voltage than the present value, then VTRIP must first be "reset" according to the procedure described below. Once VTRIP has been "reset", then VTRIP can be set to the desired voltage using the procedure described in "Setting a Higher VTRIP Voltage". Resetting the VTRIP Voltage To reset a VTRIP voltage, apply the programming voltage (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h followed by 00h for the Data Byte in order to reset VTRIP. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation. After being reset, the value of VTRIP becomes a nominal value of 1.7V or lesser. Note: This operation does not corrupt the memory array.
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X4043, X4045
Figure 3. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V, WEL bit set)
WP VP = 15-18V
01234567 SCL
01234567
01234567
SDA A0h 03h 00h
Figure 4. Sample VTRIP Reset Circuit
VP 4.7K RESET VTRIP Adj. 1 2 3 X4043 4 8 7 6 5 Run SCL SDA Adjust C
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FN8118.1 September 30, 2005
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Figure 5. VTRIP Programming Sequence
VTRIP Programming Let: MDE = Maximum Desired Error
No
Desired VTRIP < Present Value ? YES Execute VTRIP Reset Sequence
MDE+ Acceptable Desired Value Error Range MDE- Error = Actual - Desired
Set VCC = desired VTRIP
New VCC applied = Old VCC applied + | Error |
Execute Set Higher VTRIP Sequence
New VCC applied = Old VCC applied - | Error |
Power-down the Device
Execute Reset VTRIP Sequence
Ramp VCC
NO
Output Switches? (RESET) YES
Error < MDE-
Actual VTRIP - Desired VTRIP = Error | Error | < | MDE | DONE
Error > MDE+
Control Register The control register provides the user a mechanism for changing the block lock and watchdog timer settings. The block lock and watchdog timer bits are nonvolatile and do not change when power is removed. The control register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the control register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register".
The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X4043/45 will not acknowledge any data bytes written after the first byte is entered.
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The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. 7
0
WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watchdog timer. The options are shown below. WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time Out Period
1.4 seconds 600 milliseconds 200 milliseconds Disabled (factory setting)
6
WD1
5
WD0
4
BP1
3
BP0
2
RWEL
1
WEL
0
BP2
RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to "1" prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The block protect bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. BP2 BP1 BP0 Protected Addresses (Size)
None (factory setting) 180h - 1FFh (128 bytes) 100h - 1FFh (256 bytes) 000h - 1FFh (512 bytes) 000h - 00Fh (16 bytes) 000h - 01Fh (32 bytes) 000h - 03Fh (64 bytes) 000h - 07Fh (128 bytes)
Writing to the Control Register Changing any of the nonvolatile bits of the control register requires the following steps: - Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). - Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). - Write a value to the control register that has all the control bits set to the desired state. This can be represented as 0xys t01r in binary, where xy are the WD bits, and rst are the BP bits. (Operation preceeded by a start and ended with a stop). Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (0xys t11r) then the RWEL bit is set, but the WD1, WD0, BP2, BP1 and BP0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. - A read operation occurring between any of the previous operations will not interrupt the register write operation. - The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set.
Array Lock
None Upper 1/4 (Q4) Upper 1/2 (Q3,Q4) Full Array (All) First Page (P1) First 2 pgs (P2) First 4 pgs (P4) First 8 pgs (P8)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data Figure 6. Valid Data Changes on the SDA Bus
SCL
transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6.
SDA Data Stable Data Change Data Stable
Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 7. Figure 7. Valid Start and Stop Conditions
Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 6.
SCL
SDA Start Stop
Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 8. The device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to standby mode and place the device into a known state.
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Figure 8. Acknowledge Response From Receiver
SCL from Master Data Output from Transmitter Data Output from Receiver 1 8 9
Start
Acknowledge
X4043/45 ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: - a device type identifier that is `1010' to access the array and `1011' to access the control register. - two bits of `0'. - one bit that becomes the MSB of the address. - one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 8. - After loading the entire slave address byte from the SDA bus, the device compares the input slave byte data to the proper slave byte. Upon a correct compare, the device outputs an acknowledge on the SDA line. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition. Slave Address Byte Figure 9. X4043/45 Addressing
Array Control Reg. Slave Byte 1 0 1 0 Word Address A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 1
Operational Notes The device powers-up in the following state: - The device is in the low power standby state. - The WEL bit is set to `0'. In this state it is not possible to write to the device. - SDA pin is the input mode. - RESET signal is active for tPURST. SERIAL WRITE OPERATIONS Byte Write For a write operation, the device requires the slave address byte and a word address byte. This gives the master access to any one of the words in the array. After receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 10. A write to a protected block of memory will suppress the acknowledge bit.
0
0
A8
R/W
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Figure 10. Byte Write Sequence
Signals from the Master S t a r t Slave Address Byte Address S t o p
Data
SDA Bus Signals from the Slave
0 A C K A C K A C K
Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and Figure 11. Page Write Operation
goes back to `0' on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7 of the page that was just written. If the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time.
(1 n 16) Signals from the Master S t a r t Slave Address Byte Address Data (1) Data (n) S t o p
SDA Bus Signals from the Slave
0 A C K A C K A C K A C K
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
7 Bytes Address Pointer Ends Here Addr = 7 5 Bytes
Address =6
Address 10
Address n-1
The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowledge, and data transfer sequence.
Stops and Write Modes Stop conditions (that terminate write operations) must be sent by the master after sending at least 1 full data byte, plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected.
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FN8118.1 September 30, 2005
X4043, X4045
Acknowledge Polling The disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5kHz write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal nonvolatile cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the slave address byte for a write or read operation. If the device is still busy with the nonvolatile cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 13. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the slave address byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 13 for the address, acknowledge, and data transfer sequence. Figure 14. Current Address Read Sequence
Signals from the Master SDA Bus Signals from the Slave S t a r t Slave Address S t o p 1 A C K
Figure 13. Acknowledge Polling Sequence
Byte Load Completed by Issuing STOP. Enter ACK Polling
Issue START
Issue Slave Address Byte (Read or Write)
Issue STOP
NO ACK Returned? YES NO Issue STOP
Nonvolatile Cycle Complete. Continue Command
YES Continue Normal Read or Write Command Sequence
PROCEED
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
Data
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FN8118.1 September 30, 2005
X4043, X4045
Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipts Figure 15. Random Address Read Sequence
Signals from the Master S t a r t Slave Address Byte Address S t a r t Slave Address S t o p 1 A C K A C K A C K
of the word address bytes, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 15 for the address, acknowledge, and data transfer sequence.
SDA Bus Signals from the Slave
0
Data
There is a similar operation, called "Set Current Address" where the device does no operation, but enters a new address into the address counter if a stop is issued instead of the second start shown in Figure 14. The device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. The next current address read operation reads from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, Figure 16. Sequential Read Sequence
Signals from the Master Slave Address
the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to address 0000H and the device continues to output data for each acknowledge received. Refer to Figure 16 for the acknowledge and data transfer sequence.
A C K
A C K
A C K
S t o p
SDA Bus
1 A C K
Signals from the Slave
Data (1)
Data (2)
Data (n-1)
Data (n)
(n is any integer greater than 1)
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FN8118.1 September 30, 2005
X4043, X4045
Data Protection The following circuitry has been included to prevent inadvertent writes: - The WEL bit must be set to allow write operations. - The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. - A three step sequence is required before writing into the control register to change watchdog timer or block lock settings. - The WP pin, when held HIGH, prevents all writes to the array and the control register. - Communication to the device is inhibited as a result of a low voltage condition (VCC < VTRIP)any inprogress communication is terminated. - Block lock bits can protect sections of the memory array from write operations. Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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FN8118.1 September 30, 2005
X4043, X4045
ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65C to +135C Storage temperature ........................ -65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. 70C +85C Option -2.7 and -2.7A Blank and -4.5A Supply Voltage Limits 2.7V to 5.5V 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) VCC = 2.7 to 5.5V Symbol
ICC1 ICC2 ISB1
(1) (1)
Parameter
Active supply current read Active supply current write Standby current AC (WDT off)
Min.
Max.
1.0 3.0 1
Unit
mA mA A
Test Conditions
VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHz VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL= 400kHz, SDA = open VCC = 1.22 x VCC min VSDA = VSCL = VSB Others = GND or VSB VSDA =VSCL = VSB Others = GND or VSB VIN = GND to VCC VSDA = GND to VCC device is in standby
(2)
ISB2(2) ISB3(2) ILI ILO VIL(3) VIH(3) VHYS
Standby current DC (WDT off) Standby current DC (WDT on) Input leakage current Output leakage current Input LOW voltage Input nonvolatile Schmitt trigger input hysteresis Fixed input level VCC related level Output LOW voltage -0.5 VCC x 0.7 0.2 .05 x VCC
1 20 10 10 VCC x 0.3 VCC + 0.5
A A A A V V V V
VOL
0.4
V
IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.0-3.6V)
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) VIL min. and VIH max. are for reference only and are not tested.
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FN8118.1 September 30, 2005
X4043, X4045
CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5V) Symbol
COUT
(4)
Parameter
Output capacitance (SDA, RESET/RESET) Input capacitance (SCL, WP)
Max.
8 6
Unit
pF pF
Test Conditions
VOUT = 0V VIN = 0V
CIN(4)
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
5V For VOL= 0.4V and IOL = 3 mA RESET 100pF 100pF 5V 1533 SDA 4.6k
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing levels Output load 0.1 VCC to 0.9 VCC 10ns 0.5 VCC Standard output load
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) 100kHz Symbol
fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU:WP tHD:WP Cb SCL clock frequency Pulse width suppression time at inputs SCL LOW to SDA data out valid Time the bus free before start of new transmission Clock LOW time Clock HIGH time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time Data output hold time SDA and SCL rise time SDA and SCL fall time WP setup time WP hold time Capacitive load for each bus line 0.4 0 400
400kHz Min.
0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 0.9
Parameter
Min.
0 n/a 0.1 4.7 4.7 4.0 4.7 4.0 250 5.0 0.6 50
Max.
100 n/a 0.9
Max.
400
Unit
kHz ns s s s s s s ns s s ns
1000 300
20 +
.1Cb(6) 0.6 0
300 300
ns ns s s
20 + .1Cb(6)
400
pF
Notes: (5) Typical values are for TA = 25C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF.
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FN8118.1 September 30, 2005
X4043, X4045
TIMING DIAGRAMS Bus Timing
tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA OUT
tDH
tBUF
WP Pin Timing
START SCL Clk 1 Slave Address Byte SDA IN tSU:WP WP tHD:WP Clk 9
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
Nonvolatile Write Cycle Timing Symbol
tWC
(7)
Parameter
Write cycle time
Min.
Typ.(7)
5
Max.
10
Unit
ms
Notes: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
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FN8118.1 September 30, 2005
X4043, X4045
Power-Up and Power-Down Timing
VTRIP VCC 0 Volts tR tPURST tRPD tPURST tF
RESET (X4043)
VRVALID
RESET (X4045)
VRVALID
RESET Output Timing Symbol
VTRIP
Parameter
Reset trip point voltage, X4043/45-4.5A Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point voltage, X4043/45-2.7 Power-up reset time out VCC detect to RESET/RESET VCC fall time VCC rise time Reset valid VCC Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 Watchdog Time Restart pulse width Reset time out
Min.
4.5 4.25 2.85 2.55 100 20 20 1 100 450 1 1 100
Typ.
4.62 4.38 2.92 2.62 200 10
Max.
4.75 4.5 3.0 2.7 400 20
Unit
V
tPURST tRPD
(8)
ms s mV/s mV/s V
tF(8) tR(8) VRVALID tWDO
200 600 1.4 200
300 800 2 400
ms ms sec s ms
tRSP tRST
Notes: (8) This parameter is periodically sampled and not 100% tested.
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FN8118.1 September 30, 2005
X4043, X4045
Watchdog Time Out For 2-Wire Interface
Start Clockin (0 or 1) tRSP < tWDO SCL Start
SDA tRST tWDO tRST
(4043) RESET Start WDT Restart
Minimum Sequence to Reset WDT SCL
SDA
VTRIP Set/Reset Conditions
(VTRIP) VCC
tTSU WP tVPS
VP
tTHD
tVPH SCL 0 7 0 7 0 7
tVPO
SDA A0h Start 01h* sets VTRIP 03h* resets VTRIP * all others reserved 00h tWC
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FN8118.1 September 30, 2005
X4043, X4045
VTRIP Programming Specifications: VCC = 2.0-5.5V; Temperature = 25C Parameter
tVPS tVPH tTSU tTHD tWC tVPO VP VTRAN Vtv tVPS WP Program Voltage Setup time WP Program Voltage Hold time VTRIP Level Setup time VTRIP Level Hold (stable) time VTRIP Program Cycle Program Voltage Off time before next cycle Programming Voltage VTRIP Set Voltage Range VTRIP Set Voltage variation after programming (-40 to +85C). WP Program Voltage Setup time
Description
Min.
10 10 10 10 10 1 15 2.0 -25 10
Max.
Unit
s s s s ms ms
18 4.75 +25
V V mV s
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FN8118.1 September 30, 2005
X4043, X4045
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8118.1 September 30, 2005
X4043, X4045
PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.025" Typical 0.220"
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
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FN8118.1 September 30, 2005
X4043, X4045
PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 24
FN8118.1 September 30, 2005

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